1. Field of the Invention
The present invention relates to a test apparatus for testing a device-under-test such as a semiconductor circuit, a program for operating the test apparatus and a recording medium for storing the program. More specifically, the invention relates to a test apparatus having a plurality of channels for receiving output signals outputted from the device-under-test.
2. Related Art
Conventionally, as a test apparatus for testing a device-under-test, there has been known a test apparatus having a plurality of channels for receiving output signals outputted from the device-under-test. Each of the channels is provided in correspondence to a plurality of output pins of the device-under-test to receive the output signal outputted from the corresponding output pin. Each channel also samples the received output signal and the test apparatus judges whether the device-under-test is defect-free based on the sampling result.
In sampling the output signal in each channel, there has to be a desirable phase difference to the output signal in the sampling timing. In detecting edges of the output signal for example, a phase difference between a sampling clock and the output signal is sequentially changed.
To that end, the test apparatus uses a source synchronous clock outputted from the device-under-test in synchronism with the output signal to sample the output signal. For example, the test apparatus generates a sampling clock synchronized with the source synchronous clock and delays the sampling clock corresponding to a desirable phase difference. Thereby, the test apparatus generates the sampling clock having the desirable phase difference to the output signal.
Still more, because the sampling of the output signal is carried out in each channel, the source synchronous clock is fed also to each channel. In the conventional test apparatus, the source synchronous clock is fed to a master channel among the plurality of channels of the test apparatus and is then distributed sequentially from the master channel to each of slave channels connected in cascade.
However, because the channels are connected each other by connectors, cables and the like, a frequency band of signal capable of passing such connection route is limited due to parasitic capacity and others of the connection route. Therefore, it has been difficult to accurately distribute the source synchronous clock to the slave channels when frequency of the source synchronous clock is high.
The frequency band of the connector connecting the channels is around 1 GHz, so that it has been difficult to pass the source synchronous clock outputted from a semiconductor chip of these days whose speed is being remarkably increased in particular. Therefore, it has been difficult to distribute the source synchronous clock to the slave channels and to test the device-under-test accurately.